A petri-net model for loop scheduling /

This thesis describes a compile-time loop scheduling scheme and a supplementary storage reduction scheme to generate code for computer architectures which exploit fine-grain parallelism, such as superscalar, VLIW, and superpipeline machines. === In the first part we propose a new loop scheduling tec...

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Bibliographic Details
Main Author: Wong, Yue-Bong
Format: Others
Language:en
Published: McGill University 1991
Subjects:
Online Access:http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=60692