High-speed Viterbi decoder design and implementation with FPGA
This thesis describes a design and implementation of a Viterbi decoder using FPGA technology. We use the sliding block filtering concept, the pipeline interleaving technique and the forward processing method to construct the design. We use VHDL to describe the design, Synopsys tools to synthesize i...
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| Language: | en_US |
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2007
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| Online Access: | http://hdl.handle.net/1993/2007 |