Design and implementation of low-latency, low-power reconfigurable on-chip networks
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017. === Cataloged from PDF version of thesis. === Includes bibliographical references (pages [159]-187). === In this dissertation, I tackle large, low-latency, low-power on-chip networ...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | English |
| Published: |
Massachusetts Institute of Technology
2017
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/109002 |