Latency reduction techniques in chip multiprocessor cache systems
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. === Includes bibliographical references (p. 117-122). === Single-chip multiprocessors (CMPs) solve several bottlenecks facing chip designers today. Compared to traditional superscalars...
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| Format: | Others |
| Language: | English |
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Massachusetts Institute of Technology
2007
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| Online Access: | http://hdl.handle.net/1721.1/36183 |