3-dimensional modeling and simulation of surface and sidewall roughening during plasma etching
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Chemical Engineering, 2008. === Includes bibliographical references. === Line edge roughness (LER) on the sidewalls of gate electrodes in metal oxide semiconductor transistors is one of the most important issues in the manufacturing of...
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| Format: | Others |
| Language: | English |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://hdl.handle.net/1721.1/43201 |