High level compilation for gate reconfigurable architectures
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001. === Includes bibliographical references (p. 205-215). === A continuing exponential increase in the number of programmable elements is turning management of gate-reconfigurable architec...
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| Format: | Others |
| Language: | English |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/8217 |