A high-speed reduced-size adder under left-to-right input arrival

A high-speed reduced-size adder under left-to-right input arrival

Bibliographic Details
Main Authors: 高木, 直史, Takagi, Naofumi
Language:en_US
Published: IEEE 1999
Subjects:
Arithmetic circuit
adder
on-the-fly conversion
divider
Online Access:http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=743413
http://hdl.handle.net/2237/5290

Internet

http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=743413
http://hdl.handle.net/2237/5290

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