A high-speed reduced-size adder under left-to-right input arrival
| Main Authors: | , |
|---|---|
| Language: | en_US |
| Published: |
IEEE
1999
|
| Subjects: | |
| Online Access: | http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=743413 http://hdl.handle.net/2237/5290 |
| id |
ndltd-NAGOYA-oai-ir.nul.nagoya-u.ac.jp-2237-5290 |
|---|---|
| record_format |
oai_dc |
| spelling |
ndltd-NAGOYA-oai-ir.nul.nagoya-u.ac.jp-2237-52902013-01-07T23:40:02ZA high-speed reduced-size adder under left-to-right input arrival高木, 直史Takagi, NaofumiArithmetic circuitadderon-the-fly conversiondividerIEEE1999-01Article(publisher)http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=743413http://hdl.handle.net/2237/529000189340IEEE Transactions on computers. v.48, n.1, Jan. 1999, p.76-80en_USCopyright c 2005 IEEE. Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. |
| collection |
NDLTD |
| language |
en_US |
| sources |
NDLTD |
| topic |
Arithmetic circuit adder on-the-fly conversion divider |
| spellingShingle |
Arithmetic circuit adder on-the-fly conversion divider 高木, 直史 Takagi, Naofumi A high-speed reduced-size adder under left-to-right input arrival |
| author |
高木, 直史 Takagi, Naofumi |
| author_facet |
高木, 直史 Takagi, Naofumi |
| author_sort |
高木, 直史 |
| title |
A high-speed reduced-size adder under left-to-right input arrival |
| title_short |
A high-speed reduced-size adder under left-to-right input arrival |
| title_full |
A high-speed reduced-size adder under left-to-right input arrival |
| title_fullStr |
A high-speed reduced-size adder under left-to-right input arrival |
| title_full_unstemmed |
A high-speed reduced-size adder under left-to-right input arrival |
| title_sort |
high-speed reduced-size adder under left-to-right input arrival |
| publisher |
IEEE |
| publishDate |
1999 |
| url |
http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=743413 http://hdl.handle.net/2237/5290 |
| work_keys_str_mv |
AT gāomùzhíshǐ ahighspeedreducedsizeadderunderlefttorightinputarrival AT takaginaofumi ahighspeedreducedsizeadderunderlefttorightinputarrival AT gāomùzhíshǐ highspeedreducedsizeadderunderlefttorightinputarrival AT takaginaofumi highspeedreducedsizeadderunderlefttorightinputarrival |
| _version_ |
1716490592560611328 |