45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is adde...
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| Online Access: | http://hdl.handle.net/2047/d20002106 |