An Area-Efficient Architecture for the Implementation of LDPC Decoder

An Area-Efficient Architecture for the Implementation of LDPC Decoder

Bibliographic Details
Main Author: Yang, Lan
Language:English
Published: Case Western Reserve University School of Graduate Studies / OhioLINK 2011
Subjects:
Computer Engineering
Low-density parity-check (LDPC) codes
Partial parallel
Error Correcting Code Decoder
FPGA implementation
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576

Internet

http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576

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