A BIST Architecture for Testing LUTs in a Virtex-4 FPGA

A BIST Architecture for Testing LUTs in a Virtex-4 FPGA

Bibliographic Details
Main Author: Gadde, Priyanka
Language:English
Published: University of Toledo / OhioLINK 2013
Subjects:
Electrical Engineering
BIST
SRAM
Faults
Memory
Virtex-4 FPGA
Read Faults
Write Faults
Built in Self-Test
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199

Internet

http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199

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