Scalable Hardware Architecture for Memristor Based Artificial Neural Network Systems

Scalable Hardware Architecture for Memristor Based Artificial Neural Network Systems

Bibliographic Details
Main Author: Ponnileth Rajendran, Ananthakrishnan
Language:English
Published: University of Cincinnati / OhioLINK 2016
Subjects:
Computer Engineering
Memristor
Artificial Neural Network
Hardware
Architecture
Bridge Synapse
Memristive
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=ucin1468509625

Internet

http://rave.ohiolink.edu/etdc/view?acc_num=ucin1468509625

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