Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic

Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic

Bibliographic Details
Main Author: Yelamarthi, Kumar
Language:English
Published: Wright State University / OhioLINK 2008
Subjects:
Electrical Engineering
process variation
adders
transistor sizing
mixed-static-dynamic
timing optimization
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=wright1213880942

Internet

http://rave.ohiolink.edu/etdc/view?acc_num=wright1213880942

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