Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits

Bibliographic Details
Main Author:	Buzakuk, Ramadan U.
Language:	English
Published:	Wright State University / OhioLINK 2011
Subjects:	Electrical Engineering Engineering
Online Access:	http://rave.ohiolink.edu/etdc/view?acc_num=wright1323911178

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spelling	ndltd-OhioLink-oai-etd.ohiolink.edu-wright13239111782021-08-03T06:17:26Z Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits Buzakuk, Ramadan U. Electrical Engineering Engineering Dynamic CMOS circuits are used in microprocessors as well as in circuits that require high speed and small areas. Dynamic CMOS circuits have many advantages but are not robust in noise tolerance in comparison with the legacy static CMOS circuits. In this thesis several noise tolerance techniques that can be implemented with Dynamic CMOS circuits for robust noise tolerance are studied. A dynamic footed with clock overlapping technique integrated with a load balancing multiple-path transistor sizing algorithm for optimizing performance of noise tolerance and speed while in consideration of process variations is presented. Using the 2-bit weighted binary-to-thermometric converter implemented in 130-nanometer CMOS process as a benchmark circuit, noise tolerance and speed measurements were conducted by Monte-Carlo simulation in process variations. The input noise tolerance for the benchmark circuit was improved by 75%. The worst-case delay and standard deviation in process variations were improved by 52.2% and 53.5%, respectively. 2011-12-15 English text Wright State University / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=wright1323911178 http://rave.ohiolink.edu/etdc/view?acc_num=wright1323911178 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection	NDLTD
language	English
sources	NDLTD
topic	Electrical Engineering Engineering
spellingShingle	Electrical Engineering Engineering Buzakuk, Ramadan U. Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits
author	Buzakuk, Ramadan U.
author_facet	Buzakuk, Ramadan U.
author_sort	Buzakuk, Ramadan U.
title	Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits
title_short	Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits
title_full	Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits
title_fullStr	Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits
title_full_unstemmed	Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits
title_sort	dynamic footed with clock overlapping and load balancing in multiple paths for noise tolerance in dynamic cmos circuits
publisher	Wright State University / OhioLINK
publishDate	2011
url	http://rave.ohiolink.edu/etdc/view?acc_num=wright1323911178
work_keys_str_mv	AT buzakukramadanu dynamicfootedwithclockoverlappingandloadbalancinginmultiplepathsfornoisetoleranceindynamiccmoscircuits
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Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits

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