Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits
Main Author: | Buzakuk, Ramadan U. |
---|---|
Language: | English |
Published: |
Wright State University / OhioLINK
2011
|
Subjects: | |
Online Access: | http://rave.ohiolink.edu/etdc/view?acc_num=wright1323911178 |
Similar Items
-
Circuit Techniques on Improving Timing and Noise in Dynamic CMOS
by: Vaidyanadeswaran, Arvind
Published: (2011) -
Design and Implementation of Noise-Tolerant Dynamic CMOS Circuit
by: Chun Wei Chang, et al.
Published: (2010) -
Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
by: Yelamarthi, Kumar
Published: (2008) -
Design considerations for minimizing noise in micropower CMOS integrated circuits
by: Larson, Bruce C. (Bruce Carl)
Published: (2008) -
Low-Noise Mixing Circuits in CMOS Microwave Integrated Circuits
by: HO, STANLEY
Published: (2009)