An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology

An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology

Bibliographic Details
Main Author: Munugala, Anvesh
Language:English
Published: Youngstown State University / OhioLINK 2018
Subjects:
Computer Engineering
Electrical Engineering
Serial communication
ASIC design
Synopsys tools
FPGA
UART
Fabrication
Design for Testability
500 nm CMOS technology
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399

Internet

http://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399

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