Layout regularity for design and manufacturability
In nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, but also decreasing manufacturing yield. On the other hand, circuit designers a...
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| Format: | Doctoral Thesis |
| Language: | English |
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Universitat Politècnica de Catalunya
2012
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| Online Access: | http://hdl.handle.net/10803/96983 |