Scaling SAT-based Automated Design Debugging with Formal Methods
The size and complexity of modern VLSI computer chips are growing at a rapid pace. Functional debugging is increasingly becoming a bottleneck in the design flow where it can take up to 60% of the total verification time. Scaling existing automated debugging tools is necessary in order to continue al...
| Main Author: | |
|---|---|
| Other Authors: | |
| Language: | en_ca |
| Published: |
2009
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1807/18789 |