Improvements to Field-Programmable Gate Array Design Efficiency using Logic Synthesis
As Field-Programmable Gate Array (FPGA) capacity can now support several processors on a single device, the scalability of FPGA design tools and methods has emerged as a major obstacle for the wider use of FPGAs. For example, logic synthesis, which has traditionally been the fastest step in the FPGA...
| Main Author: | |
|---|---|
| Other Authors: | |
| Language: | en_ca |
| Published: |
2009
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1807/19053 |