Glitch Reduction and CAD Algorithm Noise in FPGAs
This thesis presents two contributions to the FPGA CAD domain. First, a study of glitch power in a commercial FPGA is presented, showing that glitch power in FPGAs is significant. A CAD algorithm is presented that reduces glitch power at the post-routing stage by taking advantage of don't-cares...
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| Language: | en_ca |
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2011
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| Online Access: | http://hdl.handle.net/1807/31442 |