| Summary: | This thesis presents two contributions to the FPGA CAD domain. First, a study of
glitch power in a commercial FPGA is presented, showing that glitch power in FPGAs is significant. A CAD algorithm is presented that reduces glitch power at the post-routing stage by taking advantage of don't-cares in the logic functions of the circuit. This method comes at no cost to area or performance.
The second contribution of this thesis is a study of FPGA CAD algorithm noise {random choices which can have an unpredictable effect on the circuit as a whole. An analysis of noise in the logic synthesis, technology mapping, and placement stages is presented. A series of early performance and power metrics is proposed, in an effort to find the best circuit implementation in the noise space.
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