High Speed Architectures of DFT System Suitable for VLSI Implementation
碩士 === 國立交通大學 === 電子研究所 === 75 === In this thesis, some high speed architectures for DFT computation are proposed which are suitable for VLSI system implementation. One type of DFT architectures are based on matrix representation of DFT and no fast Fourier transform algorithm is used. These a...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1987
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| Online Access: | http://ndltd.ncl.edu.tw/handle/17850251992943496049 |