A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays
碩士 === 國立成功大學 === 電機工程研究所 === 81 === In this thesis, we present a graph-based technology mapping algorithm that minimize the delay of combinational circuits implemented with lookup table-based Field Programmable Gate Arrays(FPGA) architectu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1993
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| Online Access: | http://ndltd.ncl.edu.tw/handle/05920234571460349653 |