A low voltage, high speed CMOS programmable counter design for frequency synthesizer
碩士 === 國立交通大學 === 電子研究所 === 81 === This thesis deals with the design of a low voltage, high speed CMOS programmable frequency counter design. It is the heart of a frequency synthesizer IC because the speed limitation and power consumption o...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1993
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53752357641850990710 |