Analysis and Design of a New EEPROM Device
碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, a new EEPROM cell using the p-channel poly- Si TFT for erasure operation is proposed and analyzed. The TFT device is fabricated on the seond poly-silicon layer of conven- tional stacked-gat...
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ndltd-TW-082NCTU04300402016-07-18T04:09:35Z http://ndltd.ncl.edu.tw/handle/31337573063379854614 Analysis and Design of a New EEPROM Device 新型電擦拭可程式化僅讀記憶器元件之分析及設計 Cheng-Yi Yang 楊正一 碩士 國立交通大學 電子研究所 82 In this thesis, a new EEPROM cell using the p-channel poly- Si TFT for erasure operation is proposed and analyzed. The TFT device is fabricated on the seond poly-silicon layer of conven- tional stacked-gate flash EEPROM. In the proposed new EEPROM device, the hot-hole injection from the TFT device to the float- ing gate is used for cell erasure. Since the hot-hole generation in the short channel p-channel TFT devices is more serious than that in the single-crystalline MOSFETs, an effective erasure is expected. In addition, the different program/erase paths in our device can reduce the occurrence of oxide breakdown and increase the reliability. The proposed cell can be used as the normal EEPROM cell and the flash EEPROM cell. From the simulation re- sults using the TMA MEDICI simulator, the erase operation has been verified. It is shown thatthe erase time can be reduced to tens of microseconds with the comparable erasing voltages as in the conventional EEPROM. Future researches on device optimiza- tion, experimental verification, and real EEPROM design will be done. Chung-Yu Wu 吳重雨 1994 學位論文 ; thesis 93 en_US |
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碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, a new EEPROM cell using the p-channel poly- Si
TFT for erasure operation is proposed and analyzed. The TFT
device is fabricated on the seond poly-silicon layer of conven-
tional stacked-gate flash EEPROM. In the proposed new EEPROM
device, the hot-hole injection from the TFT device to the
float- ing gate is used for cell erasure. Since the hot-hole
generation in the short channel p-channel TFT devices is more
serious than that in the single-crystalline MOSFETs, an
effective erasure is expected. In addition, the different
program/erase paths in our device can reduce the occurrence of
oxide breakdown and increase the reliability. The proposed cell
can be used as the normal EEPROM cell and the flash EEPROM
cell. From the simulation re- sults using the TMA MEDICI
simulator, the erase operation has been verified. It is shown
thatthe erase time can be reduced to tens of microseconds with
the comparable erasing voltages as in the conventional EEPROM.
Future researches on device optimiza- tion, experimental
verification, and real EEPROM design will be done.
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author2 |
Chung-Yu Wu |
author_facet |
Chung-Yu Wu Cheng-Yi Yang 楊正一 |
author |
Cheng-Yi Yang 楊正一 |
spellingShingle |
Cheng-Yi Yang 楊正一 Analysis and Design of a New EEPROM Device |
author_sort |
Cheng-Yi Yang |
title |
Analysis and Design of a New EEPROM Device |
title_short |
Analysis and Design of a New EEPROM Device |
title_full |
Analysis and Design of a New EEPROM Device |
title_fullStr |
Analysis and Design of a New EEPROM Device |
title_full_unstemmed |
Analysis and Design of a New EEPROM Device |
title_sort |
analysis and design of a new eeprom device |
publishDate |
1994 |
url |
http://ndltd.ncl.edu.tw/handle/31337573063379854614 |
work_keys_str_mv |
AT chengyiyang analysisanddesignofaneweepromdevice AT yángzhèngyī analysisanddesignofaneweepromdevice AT chengyiyang xīnxíngdiàncāshìkěchéngshìhuàjǐndújìyìqìyuánjiànzhīfēnxījíshèjì AT yángzhèngyī xīnxíngdiàncāshìkěchéngshìhuàjǐndújìyìqìyuánjiànzhīfēnxījíshèjì |
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