Analysis and Design of a New EEPROM Device

• Main Authors: Cheng-Yi Yang, 楊正一
• Other Authors: Chung-Yu Wu
• Format: Others
• Language: en_US
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/31337573063379854614

碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, a new EEPROM cell using the p-channel poly- Si TFT for erasure operation is proposed and analyzed. The TFT device is fabricated on the seond poly-silicon layer of conven- tional stacked-gate flash EEPROM. In the proposed new EEPROM device, the hot-hole injection from the TFT device to the float- ing gate is used for cell erasure. Since the hot-hole generation in the short channel p-channel TFT devices is more serious than that in the single-crystalline MOSFETs, an effective erasure is expected. In addition, the different program/erase paths in our device can reduce the occurrence of oxide breakdown and increase the reliability. The proposed cell can be used as the normal EEPROM cell and the flash EEPROM cell. From the simulation re- sults using the TMA MEDICI simulator, the erase operation has been verified. It is shown thatthe erase time can be reduced to tens of microseconds with the comparable erasing voltages as in the conventional EEPROM. Future researches on device optimiza- tion, experimental verification, and real EEPROM design will be done.