An Efficient Programmable Viterbi Decoder
碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, an algorithm and an ASIC architecture for programmable Viterbi decoder are presented. This system theoretically could be driven by 100MHz singal phase clock, and has the programmable abilit...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53607334335257479375 |