| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, an algorithm and an ASIC architecture for
programmable Viterbi decoder are presented. This system
theoretically could be driven by 100MHz singal phase clock, and
has the programmable ability to decode 2 ≦ m ≦ 4
convolutional code. The efficient design comes from the
reduction of memory area, wiring area, and the speed up of add-
compare-select(ACS) operation. The trace-back method is applied
to reduce the wiring area. The path memory which stores the
surving paths is reduced as the node register cell is one bit
cell. And the SRAM cell is designed in an asymmetric way to
apply the one port in, one port out operation. This will also
reduce the memory size. And the 2-ACS's parallel processing,
together with the internal pipeline schedule of ACS unit
enchances the ACS operation speed. The architecture is then
mapped on circuit design, and layout implementation is made by
using TSMC 0.8mm CMOS SPDM technology. The chip area is
0.4cm*0.3cm and the maximum clock rate is 100MHz. In the end of
the thesis, we will discuss the ways to design the programmable
Viterbi decoder for versatile use.
|
|---|
