Power simulation for DSP architectures
碩士 === 國立交通大學 === 電子研究所 === 82 === In this paper, we present a new power simulation envi- ronment which can accept the hierarchical descriptions. It is used for chip level designs which is too complex to use the circuit level simulato...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15351259292340620144 |