The Behavior of Bilateral Latch-Up Triggering in VLSI CMOS Protection Circuits
博士 === 國立交通大學 === 電子研究所 === 82 === The results of serial studies on the behavior of bilateral latch-up in CMOS protection circuits are presented. Latch-up and ESD problems are two major factors that degrade VLSI pro- duct reliability. A new latch-up pheno...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1993
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29247230366336779482 |