Automatic Gain Control VLSI Architecture for ADSL-1 CAP System
碩士 === 國立中央大學 === 資訊及電子工程研究所 === 82 === A mixed analog-digital AGC (Automatic Gain Control) VLSI architecture for ADSL-1 (Asymmetric Digital Subscriber Line) CAP (Carrierless Amplitude/Phase Modulation) is proposed. Key analog components of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63922009811166993603 |