The Design of an Adaptive On-Line Arithmetic Code Codec Chip
碩士 === 國立成功大學 === 電機工程研究所 === 83 === In this paper, we describe the design and implementation of a CMOS VLSI chip for data compression and decompression using adaptive arithmetic codes. During the design process, the systematic design metho...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1995
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/85018547647211345968 |