The Design of an Adaptive On-Line Arithmetic Code Codec Chip

• Main Authors: Yuh-Lin Chen, 陳昱霖
• Other Authors: Jer-Min Jou
• Format: Others
• Language: zh-TW
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/85018547647211345968

碩士 === 國立成功大學 === 電機工程研究所 === 83 === In this paper, we describe the design and implementation of a CMOS VLSI chip for data compression and decompression using adaptive arithmetic codes. During the design process, the systematic design methodology of high level synthesis is applied so that both of the minimum of hardware resource and the maximum of processing speed about the chip are compromised soundly. The chip implements a new flexible modeler which estimates the probabilities of binary symbols efficiently using the table-look- up approach by 1024 bytes SRAM for the adaptor and 288 bytes ROM for the probability table. An asynchronous interface circuit for I/O communication of the chip is designed, thus the I/O operation and compression operation in the chip can be done simultaneously. The design for testability is used and a full scan is implemented in the chip. A prototype 0.8-micro chip has been designed and verified, and fabricated by CIC, it occupies a silicon area of 4.2*4.5 mm2. The chip can yield a compression and decompression rate of 3 Mbits/sec with a clock rate of 25 MHz.