A hierarchical layout compactor for VLSI circuits
碩士 === 國立成功大學 === 電機工程研究所 === 83 === Until now, full hierarchical layout compaction is most frequently used for VLSI circuits. Although the area it compacts is not as small as flat layout compaction, it can preserve the layout hierarchy. Thus, most of the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/08415325428064201797 |