| Summary: | 碩士 === 國立成功大學 === 電機工程研究所 === 83 === Until now, full hierarchical layout compaction is most
frequently used for VLSI circuits. Although the area it
compacts is not as small as flat layout compaction, it can
preserve the layout hierarchy. Thus, most of the current layout
compactor adopt the hierarchical technique. The constraints
that a layout compactor generates are integer linear
programming problems. Although the well-known Simplex algorithm
can be used to solve these LP problems, however, the execution
time will be intolerable for pratical applications. In this
thesis, we present a new method to perform full hierarchical
layout compaction by using graph theoretic method. This
algorithm replaces all time-consuming matrix operations in the
Simplex algorithm with efficient graph operations, so the
computation time is reduced. The simulations on some benchmark
circuits show that this approach produces very good results.
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