A bit-level systolic array for matrix multiplication and its application to autoassociative memory
碩士 === 國立成功大學 === 電機工程研究所 === 83 === In this thesis, a bit-level systolic array by two level pipelining method is proposed to implement the fast algorithm of matrix multiplication. After studting various current algorithms , in order to im...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06369411727618208389 |