A Simulation Study of Cache Coherent Clustered Multiprocessors
碩士 === 國立交通大學 === 資訊工程研究所 === 83 === In this thesis, we have designed a cache coherence protocol combining the nowaday existing SCI with Write-Once protocol for the clustered architecture, and implement it on the PROTEUS system. We also use...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50323298446738678797 |