A Simulation Study of Cache Coherent Clustered Multiprocessors
碩士 === 國立交通大學 === 資訊工程研究所 === 83 === In this thesis, we have designed a cache coherence protocol combining the nowaday existing SCI with Write-Once protocol for the clustered architecture, and implement it on the PROTEUS system. We also use...
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| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50323298446738678797 |
| Summary: | 碩士 === 國立交通大學 === 資訊工程研究所 === 83 === In this thesis, we have designed a cache coherence protocol
combining the nowaday existing SCI with Write-Once protocol for
the clustered architecture, and implement it on the PROTEUS
system. We also use it to evaluate the performance of the
cluster and find that the performance of the cluster is the
best on heavily memory loaded benchmarks. Because the bus can
not well service a large number of access contentions, the
performance of a bus system is worse than that of the cluster.
The network system works worse than cluster with a large number
of processors due to the long memory access latency through the
large interconnection network. For those lightly memory loaded
benchmarks, the bus system works best. It is because the
bandwidth of the bus can easily meet the requirements of memory
accesses. The cluster system works better than the network
system because of the smaller size of interconnection network.
These important results can be referred to the system designers.
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