Characterization and modeling of parasitic BJT in CMOS technology
碩士 === 國立交通大學 === 電子研究所 === 83 === In this thesis, lateral parasitic BJT's in the standard CMOS technology were characterized and modeled. An analytical expression was derived to study the layout geometric effects on the performance of...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
1995
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Online Access: | http://ndltd.ncl.edu.tw/handle/25800380281119259911 |