Analysis and design of CMOS capacitor-coupled electrostatic discharging (ESD) protection circuit

• Main Authors: Tao Cheng, 鄭道
• Other Authors: Chung-Yu Wu, Ming-Dou Ker
• Format: Others
• Language: en_US
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/59964843371468245198

碩士 === 國立交通大學 === 電子研究所 === 83 === An electrostatic discharging (ESD) protection circuit using the capacitor-coupled technique is proposed in this thesis. In protection circuit, the capacitor-coupled technique is utlized not only to lower the snapback-trigger voltage but to ensure homogenoues current flow in the ESD protection MOSFET. Thus the thinner gate oxide of the input MOSFETs in submicron CMOS tech- nology can be effectively protected. On the other hand, the ESD failure threshold can also be increased. A simple and accurate design model for the capacitor-coupled ESD protection circuit has been derived from physical timing analysis and verified by both SPICE simulation and experimental results in 3.3-V 0.5-μm SRAM CMOS technology. The ESD testing results and failure behavior under different design parameters have also been measured and analyzed. Both model calculations and experimental results have shown a good consistence on various performance measures of the capacitor-coupled ESD protection circuit. Finally, a case study of whole-chip ESD protection for CMOS chips with multiple power supply pins has been investigated.