A Fault Simulator Based on Software Emulation

• Main Authors: Tzung-Ping Chou, 周宗平
• Other Authors: Chung-Len Lee
• Format: Others
• Language: en_US
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/98234692667115648923

碩士 === 國立交通大學 === 電子研究所 === 83 === In this thesis, a new fault simulation technique is presented. The technique uses software emulation to speed up the fault simulator. The keyword "Software Emulation" means that a module, which should be a netlist which describes connections for each gate at the gate level representation, is replaced by a set of software instructions. Hence fault effects can be propagated by symbolic operation. In this way, the fault effects can pass through a complex module quickly and a large amount of gate level evaluations is saved. Some traditional fault simulation techniques are modified in this work to fit the high level circuits and to speed up this fault simulator. In this way , We can take the advantage of high simulation speed of hierarchical level circuit and reverse the accuracy of the gate level circuit simulation at the same time. And the memory usage is also small in this method.