A VLSI Implementation of VLD-RLD Module for MPEG-2 Video Decoder
碩士 === 國立交通大學 === 電子研究所 === 83 === The function of the VLD-RLD module presented in this thesis is to parse the video bistream, forward the fixed length part above slice header to System Controller, demap the variable length codeword into a...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63682025000826907804 |