Analysis and Design of CMOS Analog-to-Digital Converter
碩士 === 國立交通大學 === 電子研究所 === 83 === In this thesis, an 8-bit 62.5MS/sec A/D converter designed and fabricated in a 0.8um CMOS process, is presented. The A/D converter was designed to have a sampling time of 8ns(including the nonoverlapping t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82435285176569206390 |