The Design of Parallel CMAC Neural Network Controller via FPGA chips
碩士 === 國立交通大學 === 控制工程系 === 84 === The object of this thesis is to build the CMAC controller with parallel computing capability via FPGA chip. This CMAC control system combines parallelly the tranditional PD controller and the CMAC contoller. We use the C...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/40817206235359288769 |