VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio
碩士 === 國立交通大學 === 電子研究所 === 84 === In this thesis, a combined DSL and Phase Equalizer is investigated. The DSL is a nonuniform-sampling DPLL whose phase error detector, using the arcsine function with the quadrature samples of incoming...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94958766116301569781 |