| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 84 === In this thesis, a combined DSL and Phase Equalizer is
investigated. The DSL is a nonuniform-sampling DPLL whose phase
error detector, using the arcsine function with the quadrature
samples of incoming signal, has a linearcharacteristics with a
period of 2PI. The Phase Equalizer which uses decision-directed
phase tracking method operates on the phase information only. It
avoids the multiplication operations required in most
conventional equalization algorithm. The application of the
combined DSL and Phase Equalizer to the digital cellular radio
with PI/4-DQPSK modulation is studied in this thesis.And,
afterour simulation, the combined DSL and Phase Equalizer has a
better performance in BER than the N-phase DSL system. In
addition to the software simulations, the hardware design of the
combined DSL and Phase Equalizer is realized in a gate-level.
According to the hardware simulation, the circuit design is
workable.
|
|---|
