VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio

碩士 === 國立交通大學 === 電子研究所 === 84 === In this thesis, a combined DSL and Phase Equalizer is investigated. The DSL is a nonuniform-sampling DPLL whose phase error detector, using the arcsine function with the quadrature samples of incoming...

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Bibliographic Details
Main Authors:	Chen, Ten-Szu, 陳天賜
Other Authors:	Che-Ho Wei
Format:	Others
Language:	zh-TW
Published:	1996
Online Access:	http://ndltd.ncl.edu.tw/handle/94958766116301569781

id	ndltd-TW-084NCTU0430012
record_format	oai_dc
spelling	ndltd-TW-084NCTU04300122016-02-05T04:16:36Z http://ndltd.ncl.edu.tw/handle/94958766116301569781 VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio 數位行動通訊鎖相迴路及等化器之積體電路設計 Chen, Ten-Szu 陳天賜碩士國立交通大學電子研究所 84 In this thesis, a combined DSL and Phase Equalizer is investigated. The DSL is a nonuniform-sampling DPLL whose phase error detector, using the arcsine function with the quadrature samples of incoming signal, has a linearcharacteristics with a period of 2PI. The Phase Equalizer which uses decision-directed phase tracking method operates on the phase information only. It avoids the multiplication operations required in most conventional equalization algorithm. The application of the combined DSL and Phase Equalizer to the digital cellular radio with PI/4-DQPSK modulation is studied in this thesis.And, afterour simulation, the combined DSL and Phase Equalizer has a better performance in BER than the N-phase DSL system. In addition to the software simulations, the hardware design of the combined DSL and Phase Equalizer is realized in a gate-level. According to the hardware simulation, the circuit design is workable. Che-Ho Wei 魏哲和 1996 學位論文 ; thesis 54 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電子研究所 === 84 === In this thesis, a combined DSL and Phase Equalizer is investigated. The DSL is a nonuniform-sampling DPLL whose phase error detector, using the arcsine function with the quadrature samples of incoming signal, has a linearcharacteristics with a period of 2PI. The Phase Equalizer which uses decision-directed phase tracking method operates on the phase information only. It avoids the multiplication operations required in most conventional equalization algorithm. The application of the combined DSL and Phase Equalizer to the digital cellular radio with PI/4-DQPSK modulation is studied in this thesis.And, afterour simulation, the combined DSL and Phase Equalizer has a better performance in BER than the N-phase DSL system. In addition to the software simulations, the hardware design of the combined DSL and Phase Equalizer is realized in a gate-level. According to the hardware simulation, the circuit design is workable.
author2	Che-Ho Wei
author_facet	Che-Ho Wei Chen, Ten-Szu 陳天賜
author	Chen, Ten-Szu 陳天賜
spellingShingle	Chen, Ten-Szu 陳天賜 VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio
author_sort	Chen, Ten-Szu
title	VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio
title_short	VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio
title_full	VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio
title_fullStr	VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio
title_full_unstemmed	VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio
title_sort	vlsi design of digital phase locked loop and phase equalizer for tdma mobile radio
publishDate	1996
url	http://ndltd.ncl.edu.tw/handle/94958766116301569781
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VLSI Design of Digital Phase Locked Loop and Phase Equalizer for TDMA Mobile Radio

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