Glitch Power Estimation Using Delay Variance Analysis
碩士 === 國立交通大學 === 電子研究所 === 84 === In this thesis, we propose a systematic method to estimate the partial glitch power in a delay balanced circuit. Partial glitches come from the skew of input arrival time and this skew may result from the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95175031269535069990 |