Timing Recovery Circuit Design and Implementation for Digital 8-VSB and 64-QAM Signals
碩士 === 國立交通大學 === 電信工程研究所 === 84 === In this thesis, a timing recovery method is proposed for 8-VSB and 64-QAM digital signals. We desire the recovered timing for the receiver operationhave an accurate frequency. The simulation results show that the req...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94464224056116872515 |