Timing Recovery Circuit Design and Implementation for Digital 8-VSB and 64-QAM Signals

• Main Authors: Shieh, Whieh-Jen, 謝慧珍
• Other Authors: Winston I. Way
• Format: Others
• Language: zh-TW
• Published: 1996
• Online Access: http://ndltd.ncl.edu.tw/handle/94464224056116872515

碩士 === 國立交通大學 === 電信工程研究所 === 84 === In this thesis, a timing recovery method is proposed for 8-VSB and 64-QAM digital signals. We desire the recovered timing for the receiver operationhave an accurate frequency. The simulation results show that the requirementis achieved. The timing recovery circuit processes the data signal itself, noadditional preamble or discrete tone is required. We will operate the timingrecovery in the baseband and some modification prevents the interaction withcarrier recovery is also proposed. We implement the proposed timing recoverycircuit in discrete components and construct a filter and some control circuitin FPGA.