Analysis and Comparison of Adders and Multipliers for Low Power High Speed Design
碩士 === 國立中山大學 === 資訊工程研究所 === 84 === In this thesis , speed , power , area comparison of 64-bits adders and 16*16 multipliers in both circuit level and architecture level are presented. In circuit level comparison,the recent...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83644985131005740775 |